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INTEGRATED CIRCUITS
DATA SHEET
SAA2032 Digital equalization for the tape drive processing of the DCC system
Product specification Supersedes data of February 1993 File under Integrated Circuits, Miscellaneous February 1995
Philips Semiconductors
Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
FEATURES * Analog-to-digital conversion, demultiplexing, equalization and zero crossing of time multiplexed analog read amplifier signal * Microcontroller interface * Search mode envelope, label and virgin detection of the AUX channel * Search mode tape speed measurement * Simplified external biassing * Reduced power consumption * Analog eye output * 4 V nominal operating voltage capability. ORDERING INFORMATION EXTENDED TYPE NUMBER SAA2032GP Note PACKAGE PINS 44 PIN POSITION QFP 1 MATERIAL plastic GENERAL DESCRIPTION
SAA2032
Performing the Digital Equalizing function in the Digital Compact Cassette (DCC) system, the SAA2032 is intended for use in conjunction with the SAA2022, read amplifier TDA1317 or TDA1318.
CODE SOT205AG
1. When using reflow soldering it is recommended that the Dry Packing instructions in the Quality Reference Pocketbook are followed. The pocketbook can be ordered using the code 9398 510 34011.
February 1995
2
Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SAA2032
VDDAD
VDD
11 43
12 3 RDCLK RDSYNC LABEL VIRGIN AENV CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AUX
f 24
CLOCK GENERATION
2 37
SAA2032
VIRGIN LABEL DETECTOR
36 38 22 23 24 25 26 27 28 29 30
VIN
5
ADC
DEMUX
FILTER
SLICER
1 44 15
DIGEYE VAL ANEYE
DAC 32 33 34 35 LT INTERFACE
LTENDEQ LTCNT1 LTCNT0 LTCLK
31
LTDATA
8, 14
10
13, 17, 39
MEA663
V SSA
V SSAD
V SS
Fig.1 Block diagram.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
PINNING SYMBOL DIGEYE RDSYNC RDCLK TEST1 VIN REFN REFP VSSA BIASA VSSAD VDDAD VDD VSS VSSA ANEYE n.c. VSS TEST4 TEST5 TEST6 TEST7 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AUX LTDATA LTENDEQ LTCNT1 LTCNT0 LTCLK VIRGIN LABEL AENV VSS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 serial data output for eye pattern SYNC data for Read Amplifier (push-pull output) data clock for Read Amplifier (push-pull output) test 1; to be connected to VSS analog time multiplexed input from Read Amplifier lower reference voltage (+1 V) for ADC upper reference voltage (+3.1 V) for ADC analog ground (0 V) bias current for ADC (sinks current from VDDAD via 33 k) supply ground (0 V) for ADC supply voltage (+5 V) for ADC supply voltage (+5 V) supply ground (0 V) supply ground (0 V) analog eye voltage output not connected supply ground (0 V) test 4; do not connect test 5; do not connect test 6; do not connect test 7; do not connect DESCRIPTION
SAA2032
channel 0 output for SAA2022 (DCC Drive Signal Processing) (push-pull output) channel 1 output for SAA2022 (push-pull output) channel 2 output for SAA2022 (push-pull output) channel 3 output for SAA2022 (push-pull output) channel 4 output for SAA2022 (push-pull output) channel 5 output for SAA2022 (push-pull output) channel 6 output for SAA2022 (push-pull output) channel 7 output for SAA2022 (push-pull output) AUX channel output for SAA2022 (push-pull output) microcontroller I/O data interface (3-state push-pull output and input; CMOS levels) microcontroller interface enabling (CMOS input levels) microcontroller interface; mode control 1 (CMOS input levels) microcontroller interface; mode control 0 (CMOS input levels) microcontroller bit-clock interface (CMOS input levels) search mode virgin detection output search mode label detection output search mode auxiliary detection output supply ground (0 V)
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SYMBOL TEST8 TEST9 TEST10 f24 VAL PIN 40 41 42 43 44 test 8 input; to be connected to VSS test 9 input; to be connected to VSS test 10 input; to be connected to VSS clock input; typical frequency 24.576 MHz (CMOS input) synchronization output for DIGEYE DESCRIPTION
SAA2032
44
43
42
41
40
39
38
37
36
35
34
LTCNT0
TEST10
VIRGIN
LABEL
TEST9
TEST8
AENV
VSS
VAL
LTCLK
f24
DIGEYE RDSYNC RDCLK TEST1 VIN REFN REFP VSSA BIASA VSSAD VDDAD
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29
LTCNT1 LTENDEQ LTDATA AUX CH7 CH6 CH5 CH4 CH3 CH2 CH1
SAA2032
28 27 26 25 24 23
15
16
18
20
12
13
14
17
19
21
22
n.c.
VSSA
ANEYE
V SS
TEST4
TEST5
TEST6
Fig.2 Pin configuration.
February 1995
5
TEST7
V DD
CH0
VSS
MEA661
February 1995
stereo filter codec speed control SAA2002 I 2S (sub-band) capstan drive
Philips Semiconductors
RECORDING + PLAY BACK
analog input
ADC SAA7360
analog output
DAC SAA7323
IS
2
TDA1316 or TDA1319
write
Digital equalization for the tape drive processing of the DCC system
digital input SAA2012 adaptive allocation and scale factors RAM 256 kbits SAA2022
digital output
DAIO TDA1315
SAA2032 read digital equalizer
heads and tape
6
PASC PROCESSING
MEA695 - 2
TDA1317 or TDA1318
AUDIO INPUT/OUTPUT
TAPE DRIVE PROCESSING
MICROCONTROLLER
Product specification
SAA2032
Fig.3 DCC data flow diagram.
Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
FUNCTIONAL DESCRIPTION Operating Modes DEQ operating modes are programmed via the LT interface: NORMAL * A/D conversion * Demultiplexing * Equalization * Zero crossing. in this mode the SAA2032 performs the equalization and slicing of the eight data channels and the auxiliary channel. The eight data channels have a bit-rate of 96 kbits/s while the auxiliary channel has a bit-rate of 12 kbits/s. The SAA2032 input is a time-multiplexed analog signal from the Read Amplifier. The signal contains ten time slots, of which nine are used. The Read Amplifier and the SAA2032 synchronize with the RDCLK and RDSYNC signals generated by the SAA2032. Following A/D conversion and demultiplexing the nine channels are equalized. The encoding of the equalizing coefficients (12 per channel) are not fixed and must be loaded via the LT interface before operation. The nine equalized output signals are up-sampled by a factor of 10 with the resulting signals fed to the slicer. The slicer output is applied to the SAA2022. TEST * A/D conversion * Demultiplexing * Equalization * Zero crossing * Eye-pattern. Same as normal mode. In addition the digital and analog eye-pattern outputs are enabled. The eye-pattern output corresponds to one of the equalized channel outputs. SEARCH * A/D conversion * Envelope detection * Tape search and speed measurement. In the search mode the analog input signal from the Read Amplifier is not the multiplexed signal but only the auxiliary channel signal.
SAA2032
Following A/D conversion the envelope of this signal is filtered and sliced. This forms the Alternating Envelope AENV output. The LABEL and VIRGIN outputs are detected from this and the tape search speed measured. OFF In the OFF mode the RDSYNC and RDCLK signals are HIGH, the EYE outputs are disabled and the channel and auxiliary outputs (CH0 to CH7 and AUX) are 3-stated. Read Amplifier interface The interface between the Read Amplifier and the SAA2032 consists of three signals: 1. 2. VIN from Read Amplifier to SAA2032; time multiplexed data. RDSYNC from SAA2032 to Read Amplifier; synchronization between Read Amplifier multiplexer and SAA2032 demultiplexer. RDCLK from SAA2032 to Read Amplifier; data clock for Read Amplifier multiplexer.
3.
The multiplexed VIN output of the Read Amplifier changes to another channel at the rising edge of RDCLK. RDSYNC synchronizes the Read Amplifier VIN output: if RDSYNC is HIGH, the rising edge of the RDCLK will select the AUX channel. Figures 4 and 5 show the relationship between the SAA2032 and the Read Amplifier. SAA2022 interface The interface with the SAA2022 consists of the 9 data output signals CH0 to CH7, AUX. Table 1 Dependency of Read Amplifier on operational mode. RDSYNC YES YES HIGH HIGH RDCLK YES YES YES HIGH
OPERATIONAL MODE Normal Test Search Off
Label and virgin detection interface When the DCC player is in its search mode, the tape is fast-wound while the head retains tape contact. The SAA2032 can be made to operate in the search mode and the information will be read from the auxiliary tape track.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
The following three signals are generated: 1. 2. 3. LABEL: label detection (HIGH if label is detected). VIRGIN: virgin tape detection (HIGH if virgin tape is detected). AENV: alternating envelope (sliced envelope).
SAA2032
tape speed must be known. In search mode the SAA2032 assesses the speed of labelled tapes. The microcontroller obtains this information via the LT-interface. The speed information is encoded in 3 variables: 1. 2. 3. SVF Speed Validation Flag (HIGH if invalid). SC (4..0) Speed counter.
AENV, LABEL and VIRGIN are disabled in normal or off modes. LABEL, VIRGIN and AENV are LOW. AENV, LABEL and VIRGIN are enabled when the SAA2032 is in search mode. The device detects the envelope AENV of the auxiliary track at search speeds between 3 and 50 times normal speed. If AENV is continuously HIGH (label detection), LABEL will be HIGH. When AENV is continuously LOW (virgin tape detection) VIRGIN will be HIGH. Figures 6, 7 and 8 show the relationship between AENV, VIRGIN and LABEL. Labelled tape-speed calculation When the DCC player is in its search mode, the tape speed increases. LABEL information is encoded throughout its length. To examine the length of a label, the
SR (1..0) Speed Range. 51.2 SR Search speed = 2 x ---------- x normal speed. SC If SC = 0 then search speed > 51.2. With SR = 0, 1, 2 or 3 and SC = 0 to 31. If SVF = 1 then SR and SC values are invalid.
Appendix 1 gives a table of the search mode speed control. Microcontroller (LT) Interface The SAA2032 is able to exchange information with the microcontroller via the LT-interface. The microcontroller performs as master, the SAA2032 as slave. Figure 9 gives the operation of the LT-interface.
RDCLK VIN RDSYNC
MCD477
CH7 AUX
***
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AUX
***
CH0 CH1
Fig.4 Signals on interface between Read Amplifier and SAA2032.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SAA2032
RDCLK t su VIN VIN stable
MCD478
tsu > 80 ns; set-up time VIN before RDCLOCK HIGH. Typical frequency for RDCLK = 3.072 MHz. Typical frequency for RDSYNC = 307.2 kHz. Fig.5 Timing.
signal from tape t d1 AENV
MCD488 - 1
t d2
td1 = td2 = between 0.5 and 1.0 auxiliary block lengths. Fig.6 Diagram of AENV signal.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SAA2032
AENV t d3 LABEL
MLA635 - 2
t d4
td3 = between 4 and 12 auxiliary blocks. td4 = between 4 and 12 auxiliary blocks. Fig.7 AENV and LABEL signals.
AENV t d5 VIRGIN
MLA634 - 2
t d6
td5 = td6 = between 4 and 12 auxiliary blocks. Fig.8 AENV and VIRGIN signals.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SAA2032
LTENDEQ
LTCNT 0/1
LTCLK
LTDATA 0 LSB 1 2 3 4 5 6 7 MSB
MCD479
Fig.9 Typical operation of the LT-interface.
LTCNT specification Table 2 Four types of data exchange performed on the interface. LTCNT0 0 1 0 1 data data address mode settings LT DATA EXCHANGE MODE write read write write FROM C DEQ C C TO DEQ C DEQ DEQ
LTCNT1 0 0 1 1
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
Mode Settings Load (LTCNT = 11) (See Fig.10) The 8-bits transmitted under 'mode settings load' control both the 'operation mode' and the 'data exchange type'. Table 3 a1 0 0 1 1 Table 4 b1 0 0 1 Mode settings; 'operation mode'. a0 0 1 0 1 test search off Data Read (LTCNT = 01) (See Fig.13) Mode settings; 'data exchange type'. b0 0 1 1 DATA write read read EXCHANGE coefficient coefficient envelope TYPE data data data LTDATA interpretation: OPERATION MODE normal
SAA2032
Address Information Load (LTCNT = 10) (See Fig.11) A channel/tap combination can be selected through this type of data exchange. Co-efficient Data Load (LTCNT = 00) (See Fig.12) This type of data exchange will overwrite the equalizer tap coefficient of the current selected channel/tap combination. The coefficient data for tap <0000> of the auxiliary channel should always be zero.
This type of data exchange will send information from the LTDATA register in the SAA2032 to the microcontroller. Data in the LTDATA register depends upon the current data exchange type.
* coefficient data: two's complement coefficient data Remark post condition: after every communication sequence the data exchange type must be set to "read coefficient data". * tape speed data - d7 = SVF flag - d6 to d2 = SC4 to SC0 - d1, d0 = SR1, SR0. Tape speed data format is shown in Fig.14.
MSB LSB
*
*
*
*
b1
b0
a1
a0
MCD480
data exchange type
operation mode
Fig.10 Mode settings load (LTCNT = 11).
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SAA2032
c3 MSB
c2
c1
c0
t3
t2
t1
t0
MCD481
d7 MSB
d6
d5
d4
d3
d2
d1
d0
MCD482
LSB
LSB
c3 to c0 --> channel number <0000 to 0111> + auxiliary channel <1000> t3 to t0 --> tap number <0000 .. 1011> Fig.11 Address information load (LTCNT = 10). Fig.12 Coefficient data load (LTCNT = 00).
d7 d7 MSB d6 d5 d4 d3 d2 d1 d0
MCD483
d0
MBC381
LSB SVF SC (h. . .0) SR (1. . .0)
Fig.13 Read data (LTCNT = 01).
Fig.14 Tape speed data format.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SAA2032
t Le LTENDEQ t su1 LTCNT0/1 t su4 LTCLK t su3 LTDATA bit 0 1
MCD485 - 1
t h1
t h2
t su2
t Lc
tHc
t h3
tLe > 120 ns; minimum LOW time LTENDEQ before transfer. tsu1 > 20 ns; set-up time LTCNT0/1 before LTENDEQ HIGH. th1 > 100 ns; hold time LTCNT0/1 after LTENDEQ HIGH. tsu2 0 ns; set-up time LTCNT0/1 before LTCLK LOW. th2 > 20 ns; hold time LTENDEQ after LTCLK HIGH. tLc > 120 ns; minimum LOW time LTCLK. tHc > 120 ns; minimum HIGH time LTCLK. tsu4 > 200 ns; set-up time LTCLK before LTENDEQ HIGH. tsu3 > 100 ns; set-up time LTDATA before LTCLK HIGH. th3 > 20 ns; hold time LTDATA after LTCLK HIGH. Fig.15 Microcontroller to SAA2032 timing.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SAA2032
t Le LTENDEQ t su1 LTCNT0/1 t su4 LTCLK t d1 LTDATA bit 0 1
MCD486 - 1
t h1
t h2
t su2
t Lc
tHc
t d2
t h5
t h6
tLe > 120 ns; minimum LOW time LTENDEQ before transfer. tsu1 > 20 ns; set-up time LTCNT0/1 before LTENDEQ HIGH. th1 > 100 ns; hold time LTCNT0/1 after LTENDEQ HIGH. tsu2 0 ns; set-up time LTCNT0/1 before LTCLK LOW. th2 > 20 ns; hold time LTENDEQ after LTCLK HIGH. tLc > 120 ns; minimum LOW time LTCLK. tHc > 120 ns; minimum HIGH time LTCLK. tsu4 > 200 ns; set-up time LTCLK before LTENDEQ HIGH. td1 > 300 ns; maximum delay LTDATA after LTENDEQ HIGH. td2 > 400 ns; maximum delay LTDATA after LTCLK HIGH. th5 > 160 ns; hold time LTDATA after LTCLK HIGH. th6 > 0 ns; hold time LTDA after LTENDEQ LOW. Fig.16 SAA2032 to Microcontroller timing.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
Eye pattern output To test equalization performance it is possible to output the equalized channels. For this purpose one analog and two digital output signals are provided. Selection of the EYE pattern output is determined by the last channel address sent to the SAA2032. * DIGEYE: serial data line for 8-bits output value * VAL: validation signal for data bits * ANEYE: analog eye voltage output. The eye outputs are enabled in test mode. Table 5 Eye outputs. DIGEYE LOW
SAA2032
OPERATION MODE Normal Test Search Off
ANEYE HIGH ENABLED HIGH HIGH
ENABLED LOW LOW
The internal number representation in the SAA2032 is in two's complement. The format of the selected 8-bits will be converted to the off-set-binary format. This means that the MSB of the two's complement number has been inverted. This 8-bit number is shifted out via the DIGEYE output. Figure 17 gives the eye pattern output timing.
t eye VAL
t val
RDCLK
DIGEYE LSB MSB (inverted) LSB
RDCLK t clk
th DIGEYE stable data
t su
MEA662 - 1
tval = 1/4 clock period; pulse width HIGH. tsu > 60 ns; minimum set-up time data before clock. th > 5 ns; minimum hold time data after clock. tclk = 1/fclk. fclk = 3.072 MHz; nominal DIGEYE clock frequency. teye = 1/feye. feye = 307.2 kHz; nominal DIGEYE clock frequency. Fig.17 Timing diagram.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI ISS IDD II IO Ptot Tstg Tamb Ves1 Ves2 Notes 1. Input voltage should not exceed 6.5 V unless otherwise specified. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. DC CHARACTERISTICS VDD = 3.8 to 5.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supply VDD VDDAD IDD IDDAD IOP PARAMETER supply voltage supply voltage for ADC supply current supply current for ADC operating current note 1 VDD = 5 V; note 2 VDD = 3.8 V; note 2 VDDAD = 5 V VDDAD = 3.8 V note 3 Inputs f24, LTCLK, LTCNT0, LTCNT1 and LTENDEQ LOW level input voltage VIL VIH II Input REFP Vrefp Input REFN Vrefn HIGH level input voltage input current CONDITIONS MIN. 3.8 3.8 - - - - 1.3 0 0.7VDD VI = 0 V; Tamb = 25 C - VI = VDD; Tamb = 25 C - reference voltage reference voltage 2.7 0.7 TYP. 5.0 5.0 22 12 11 5 1.9 - - - - 3.1 1.0 PARAMETER supply voltage input voltage supply current in VSS supply current in VDD input current output current total power dissipation storage temperature operating ambient temperature electrostatic handling electrostatic handling note 2 note 3 note 1 CONDITIONS MIN. -0.5 -0.5 - - -10 -20 - -55 -40 -1500 -70 MAX. +6.5
SAA2032
UNIT V V mA mA mA mA mW C C V V
VDD + 0.5 -100 100 10 20 550 +150 +85 +1500 +70
MAX. 5.5 5.5 26 14 13 7 3.4 0.3VDD VDD -10 10 3.4 1.4 V V
UNIT
mA mA mA mA mA V V A A V V
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SYMBOL Inputs REFP and REFN Vref Input VIN VI(p-p) II Digital outputs VOL VOH Output ANEYE VO VO input voltage (peak-to-peak) input current LOW level output voltage HIGH level output voltage output voltage output voltage range note 4 note 4 note 4 note 4 IO = -3 mA IO = 2 mA Vrefn - - - - - Vrefp 100 0.4 - VDDAD - 0.4 - 10 10 reference voltage difference between REFP and REFN 2 2.1 2.7 PARAMETER CONDITIONS MIN. TYP.
SAA2032
MAX.
UNIT
V
V A V V V V V V A A V V
VDD - 0.5 - - - - - 1.1 - - - - -
Input/output LTDATA VOL LOW level output voltage VOH IOZ VIL VIH Notes 1. VDDAD should never be lower than VDD - 0.2 V. HIGH level output voltage leakage current with outputs in 3-state LOW level input voltage HIGH level input voltage
VDD - 0.5 -
VI = 0 V; Tamb = 25 C - VI = VDD; Tamb = 25 C - - 0.7VDD
0.3VDD -
2. For load impedances in a typical application circuit. 3. Operating reference current for the specified range of Vrefp allowing for the tolerance on the internal resistor. 4. For outputs DIGEYE, RDSYNC, RDCLK, CH0 to CH7, AUX and VAL the maximum load current is 1 mA. For ANEYE output the maximum load current is 10 A. For VIRGIN, LABEL and AENV the maximum load current is 2 mA.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
AC CHARACTERISTICS VDD = 3.8 to 5.5 V; Tamb = -40 to 85 C; unless otherwise specified. SYMBOL VIN Ci Ci PARAMETER input capacitance input capacitance CONDITIONS - - 23 10 10 30 - - - - - - note 1 note 1 10 30 MIN. - - 24.576 - - - - - - - - - - - TYP.
SAA2032
MAX. 15 10 26 - - - 10 50 80 10 50 80 - -
UNIT pF pF MHz ns ns ns pF pF ns pF pF ns ns ns
All digital inputs Clock input f24 f clock frequency tp pulse width LOW or HIGH Inputs LTCLK, LTENDEQ, LTCNT0 and LTCNT1 set-up time to f24 note 1 tsu th All outputs Ci CL td hold time from f24 input capacitance load capacitance propagation delay time from f24 note 1 note 1
Input/output LTDATA input capacitance Ci CL td tsu th Note 1. LOW-to-HIGH transition. load capacitance propagation delay time from f24 set-up time to f24 hold time from f24
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
CONVERTER CHARACTERISTICS VDD = 3.8 to 5.5 V; Tamb = -40 to 85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS - - 6-bit resolution at fs = 3.1 MHz note 1 0.5 - 0.7 2.7 2 Vrefn note 2 21 - note 3 - - note 4 note 4 - - MIN. 7 2 x tcy - - 1.0 3.1 2.1 - - - - 6 - 1.1 TYP. - - -
SAA2032
MAX.
UNIT bits MHz LSB V V V V dB pF A bits V V
Analog-to-Digital Converter; VIN resolution conversation data available after effective input bandwidth differential non-linearity Vrefn Vrefp Vref Vi S+THD/N Ci II reference voltage at VREFN reference voltage at VREFP reference voltage difference between REFP and REFN input voltage signal-to-total harmonic distortion and noise ratio input capacitance input current (DC)
0.99 1.4 3.4 2.7 Vrefp - 15 100 - VDDAD -
Digital-to-analog converter; output ANEYE resolution VO VO Notes 1. Vrefp is supplied externally. Vrefn is derived internally and set to 1/3Vrefp. Vrefn must be decoupled externally at pin 6 via a 100 nF capacitor. 2. Signal level (fs) -20 dB, at any DC level within the input voltage range. output voltage output voltage range
3. The output impedance of the analog input signal source must be <150 . 4. Load impedance 1 M.
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
APPENDIX 1 Search Mode Speed Control Interface
SAA2032
In search mode the SAA2032 measures the tape speed. The tape speed is encapsulated in the variables: * SVF Speed Validation Flag; is HIGH if NOT valid * SC Speed Counter * SR Speed Range. The values in Table 6 represent the speed in multiples of the nominal tape speed of 4.76 cm/s. Table 6 Speed in multiples of nominal tape speed. SR[1 .. 0] 0 >51.20 51.20 25.60 17.07 12.80 10.24 8.53 7.31 6.40 5.69 5.12 4.65 4.27 3.94 3.66 3.41 3.20 3.01 1 >102.40 102.40 51.20 34.13 25.60 20.48 17.07 14.63 12.80 11.38 10.24 9.31 8.53 7.88 7.31 6.83 6.40 6.02 2 >204.80 204.80 102.40 68.27 51.20 40.96 34.13 29.26 25.60 22.76 20.48 18.62 17.07 15.75 14.63 13.65 12.80 12.05 3 >409.60 409.60 204.80 136.53 102.40 81.92 68.27 58.51 51.20 45.51 40.96 37.24 34.13 31.51 29.26 27.31 25.60 24.09 normal working area shift to higher speed range REMARKS
SC[4 .. 0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SR[1 .. 0] 0 2.84 2.69 2.56 2.44 2.33 2.23 2.13 2.05 1.97 1.90 1.83 1.77 1.71 1.65 1 5.69 5.39 5.12 4.88 4.65 4.45 4.27 4.10 3.94 3.79 3.66 3.53 4.41 3.30 2 11.38 10.78 10.24 9.75 9.31 8.90 8.53 8.19 7.88 7.59 7.31 7.06 6.83 6.61 3 22.76 21.56 20.48 19.50 18.62 17.81 17.07 16.38 15.75 15.17 14.63 14.12 13.65 13.21
SAA2032
SC[4 .. 0] 18 19 20 21 22 23 24 25 26 27 28 29 30 31
REMARKS
shift to lower speed range
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
PACKAGE OUTLINE
SAA2032
seating plane
0.15 S
S
19.2 18.2 44 34 B 2.4 (4x) 1.8
1 pin 1 index
33
1.0
11
23 0.50 0.35 12 22 2.4 1.8 (4x) 0.15 M A 14.1 13.9 X
1.0
0.50 0.35
A
0.15 M B
14.1 13.9
19.2 18.2
2.3 2.1
1.2 0.9 0.25 0.05 0.25 0.14 2.60 2.15
2.0 1.2 detail X
0 to 7 o
MBC659 - 1
Dimensions in mm. Fig.18 44-lead quad flat-pack; plastic (SOT205AG).
February 1995
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Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
SOLDERING Quad flat-packs BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two waves (dual-wave), in which, in a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement.
SAA2032
Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapourphase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
February 1995
24
Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA2032
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress rating only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.
February 1995
25
Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system NOTES
SAA2032
February 1995
26
Philips Semiconductors
Product specification
Digital equalization for the tape drive processing of the DCC system NOTES
SAA2032
February 1995
27
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)829-1166, Fax. (011)829-1849 Canada: INTEGRATED CIRCUITS: Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 601 Milner Ave, SCARBOROUGH, ONTARIO, M1B 1M8, Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: Carrera 21 No. 56-17, BOGOTA, D.E., P.O. Box 77621, Tel. (571)217 4609, Fax. (01)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20095 HAMBURG , Tel. (040)3296-0, Fax. (040)3296 213 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: 15/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, Tel. (0)4245 121, Fax. (0)4806 960 India: PEICO ELECTRONICS & ELECTRICALS Ltd., Components Dept., Shivsagar Estate, Block 'A', Dr. Annie Besant Rd., Worli, BOMBAY 400 018, Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.1, Fax. (02)6752.3350 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, KOKIO 108, Tel. (03)3740 5101, Fax. (03)3740 0570 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)757 5511, Fax. (03)757 4880 Mexico: Philips Components, 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Tel. (040)78 37 49, Fax. (040)78 83 99 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (22)74 8000, Fax. (22)74 8341 Pakistan: Philips Markaz, M.A. Jinnah Rd., KARACHI 3, Tel. (021)577 039, Fax. (021)569 1832 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 911, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: Av. Eng. Duarte Pacheco 6, 1009 LISBOA Codex, Tel. (01)683 121, Fax. (01)658 013 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: 195-215 Main Road, Martindale, P.O. Box 7430,JOHANNESBURG 2000, Tel. (011)470-5433, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 7730 Taiwan: 69, Min Sheng East Road, Sec 3, P.O. Box 22978, TAIPEI 10446, Tel. (2)509 7666, Fax. (2)500 5899 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna - Trad Road Km. 3 Prakanong, BANGKOK 10260, Tel. (2)399-3280 to 9, (2)398-2083, Fax. (2)398-2080 Turkey: Talatpasa Cad. No. 5, 80640 LEVENT/ISTANBUL, Tel. (0212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD28 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Philips Semiconductors

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